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CEC Semester Twelve 2017

FPGA Programming

Louis Giokas -
September 11,
2017
Intro –FPGA Device Description

Now that we have an algorithm developed, debugged and laid out in our design tolos we are ready to transfer that to the FPGA chip and run our algorithm there. We will also discuss the process of reprogramming the chip during operations and will discuss how that might be used.

Course Resources
Special Educational Materials
Faster Debugging Using Specialized Triggers - Rohde & Schwarz
Testing FPGA Based Hardware Emulators With Slow I/Q Signals - Rohde & Schwarz
USB Power Delivery Compliance Testing - Rohde & Schwarz
September 12,
2017
Design Flow

Now that we have an algorithm developed, debugged and laid out in our design tolos we are ready to transfer that to the FPGA chip and run our algorithm there. We will also discuss the process of reprogramming the chip during operations and will discuss how that might be used.

Course Resources
Special Educational Materials
Faster Debugging Using Specialized Triggers - Rohde & Schwarz
Testing FPGA Based Hardware Emulators With Slow I/Q Signals - Rohde & Schwarz
USB Power Delivery Compliance Testing - Rohde & Schwarz
September 13,
2017
HDL

Now that we have an algorithm developed, debugged and laid out in our design tolos we are ready to transfer that to the FPGA chip and run our algorithm there. We will also discuss the process of reprogramming the chip during operations and will discuss how that might be used.

Course Resources
Special Educational Materials
Faster Debugging Using Specialized Triggers - Rohde & Schwarz
Testing FPGA Based Hardware Emulators With Slow I/Q Signals - Rohde & Schwarz
USB Power Delivery Compliance Testing - Rohde & Schwarz
September 14,
2017
Synthesis and Layout

Now that we have an algorithm developed, debugged and laid out in our design tolos we are ready to transfer that to the FPGA chip and run our algorithm there. We will also discuss the process of reprogramming the chip during operations and will discuss how that might be used.

Course Resources
Special Educational Materials
Faster Debugging Using Specialized Triggers - Rohde & Schwarz
Testing FPGA Based Hardware Emulators With Slow I/Q Signals - Rohde & Schwarz
USB Power Delivery Compliance Testing - Rohde & Schwarz
September 15,
2017
Programming the Chip

Now that we have an algorithm developed, debugged and laid out in our design tolos we are ready to transfer that to the FPGA chip and run our algorithm there. We will also discuss the process of reprogramming the chip during operations and will discuss how that might be used.

Course Resources
Special Educational Materials
Faster Debugging Using Specialized Triggers - Rohde & Schwarz
Testing FPGA Based Hardware Emulators With Slow I/Q Signals - Rohde & Schwarz
USB Power Delivery Compliance Testing - Rohde & Schwarz
louis-giokas
Instructor
Louis Giokas

Louis Giokas started out in the aerospace business holding positions in development and management.  At General Electric Aerospace (now part of Lockheed Martin) he held positions of software engineer, systems engineer and staff engineer. While there he worked on spacecraft and military systems. Prior to that he worked for companies such as Sperry UNIVAC and Link Simulation Systems, also working or spacecraft and military systems. Over the past two decades he has worked in the database management software area for Oracle and IBM. Over the past several years he has worked on development projects and has consulted in a number of different areas, including embedded systems. He is a long-standing member of the Institute of Electrical and Electronics Engineers (IEEE). Currently, he is the secretary of the Fox Valley Subsection of the Chicago Section and chairman of the Computer Society of the Chicago Section. He has a degree in Computer Science from Villanova University and is pursuing a MS in Applied Statistics from DePaul University.