CEC Semenster Undefined
An Introduction to Functional Verification
Brian Bailey -
April 1,
2013
Fundamental Concepts
The functional verification of electronic systems consumes in excess of 50 percent of the time and resources for most complex chip designs, which certainly leaks into system design. On the first Day, we'll define the scope for the course and examine many of the fundamental concepts, terms, and methodologies that will be expanded upon later. Whether you are designing an IC or a system, these concepts will come in handy.
Course Resources
Special Educational Materials
April 2,
2013
Models & Model Execution
Verification is performed on models of the intended design, but those models can be at many different levels of abstraction and use different software or hardware to execute them. We will look at the major ones in use toDay and where they are best utilized in a design flow.
Course Resources
Special Educational Materials
April 3,
2013
Verification Methodologies
There is no single right way to perform verification. It is often described as an art rather than a science. In this section we will examine the most commonly used methodologies and the ways in which progress can be measured.
Course Resources
Special Educational Materials
April 4,
2013
SystemVerilog
SystemVerilog is becoming a very common language for functional verification. In this segment I will provide a high-level overview of the language and its capabilities.
Course Resources
Special Educational Materials
April 5,
2013
Universal Verification Methodology (UVM)
Because of the complexity of creating verification environment and the common elements that many of them require, a class library has been created to help jump-start a verification project. This provides a high-level overview of its structure and capabilities.
Course Resources
Special Educational Materials
Instructor
Brian Bailey